1. Technical Field
The present invention relates to semiconductor fabrication, and more particularly to a device and method for forming a single metal, single dielectric gate CMOS device having capping layers that are intermixed with a high dielectric constant dielectric designed to shift threshold voltage
2. Description of the Related Art
High dielectric constant (high-K) materials are one of the most important advancements pursued in Silicon Technology to enable continued scaling of metal oxide semiconductor field effect transistors (MOSFETs) among other semiconductor devices. To obtain band-edge operation of these devices a correct choice of dielectric and metal has a significant impact on device performance. However, single metal/single dielectric solutions have simplicity in integration, but not for tuning threshold voltages of complementary metal oxide semiconductor (CMOS) devices.
Capping layers have been recently investigated to obtain band edge n-type field effect transistor (nFET) and p-type field effect transistor (pFET) devices. However, there are many challenges in integrating both materials on a same wafer to obtain CMOS devices. Current schemes involve the deposition and patterning of these capping layers which can introduce additional complexity for lithographic processes and are often material specific solutions.